搜索资源列表
BPSK
- 八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。-Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.
bpsk
- 基于bpsk的vhdl语言编程与性能仿真-Based on the vhdl language bpsk programming and performance simulation
bpsk
- These code are some matlab codes for BPSK modulator and demodulator in fading channels for wireless communications
50846288C
- verilog 硬件编程实现bpsk调制-verilog hardware, programming bpsk Modulation
examples
- 二进制差分编码解码，二进制差分相移键控二进制幅移键控，二进制相移键控，二进制频移键控最小频移键控的调制与解调-Differential encoding and decoding binary, binary differential phase shift keying binary amplitude shift keying, BPSK, binary frequency shift keying Minimum Shift Keying modulation and demodulati
bpsk
- 基于能量检测的频谱感知.由于实际信道中的多径和阴影效应，单个认知用户频谱感知的性能受到影响，因此需要靠不同用户间的协同频谱感知来对抗多径和阴影效应。本设计要求在文中采用一种协作机制，即两用户进行协作频谱感知，提高主用户的检测率，减少检测时间，并且得到捷变增益。要求给出仿真结果。-spectrum sensing in cognitive radio based on energy detection.As the channels in diameter and shadow, not a si
BCH[31-16]-with-BPSK-MFSK
- comperation of performance of BCH [31 16] code with BPSK and MFSK
BPSK
- 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.
BPSK
- Use the verilog language to module the psk.
ad9850
- 介绍了用FPGA控制DDS产生任意频率范围之内的可调制正弦波，13位BPSK,ASK等。控制字由串口写入。-verilog control AD9850 to get psk ask
BPSK_receiver
- BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
DDS_BPSK
- 基于DDS的BPSK调制器设计Verilog源码- U57FA u4E8.08 u868
BPSK ASIC
- BPSK demodulator ASIC design with Toshiba 45nm lib in verilog for EE 287 Spring 2013 This is the class project for EE 287 SPring 2013
BPSK_ASIC.tar
- BPSK demodulator ASIC design with Toshiba 45nm lib in verilog for EE 287 Spring 2013
bpsk
- BPSK modulation technique for 1 sign bit and other the original output form. if input bit is 1; output is 01 if input bit is 0; output is 11
demodulation
- 基于verilog HDL的BPSK解调的FPGA实现，仿真结果验证良好。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684BPSK u89E3 u8C03 u7684FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u826F u597D u3002IDE u4E3Avivado 2014)
BPSK
- 先用Matlab理论仿真，得出滤波器系数。再用Verilog语言在ISE环境下编写程序，通过Modelsim和ChipScope进行波形仿真和引号抓取，从而提高调试的效率。通过手机发送指令来控制上下变频器的参数。(Firstly, the filter coefficients are obtained by simulation with the theory of matlab. Then the program is written in Verilog language under IS